1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and manufacturing method thereof. More specifically, the present invention relates to a memory structure in a non-volatile semiconductor memory device and manufacturing method thereof.
2. Description of the Background Art
FIG. 14 shows an example of a memory cell structure of a conventional non-volatile semiconductor memory device. Referring to FIG. 14 N+ diffusion layers 2 are formed spaced from each other at a main surface of a semiconductor substrate 1. An access gate and a floating gate are provided partially overlapping N+ diffusion layers 2. The access gate is formed of a polycrystalline silicon film 18, and the floating gate is formed of a polycrystalline silicon film 6.
A silicon oxide film 19 is formed to cover polycrystalline silicon film 18, and a silicon oxide film 15 is formed to cover polycrystalline silicon film 6. On the access gate and the floating gate, a conductive film (control gate) 16 is formed, and on the conductive film 16, a silicon oxide film 17 is formed.
The method of manufacturing the non-volatile semiconductor memory device shown in FIG. 14 will be described with reference to FIGS. 15 to 21.
As shown in FIG. 15, on the main surface of semiconductor substrate 1, silicon oxide film 5 is grown by thermal oxidation. Thereafter, a phosphorus doped polycrystalline silicon film 6 is grown by CVD (Chemical Vapor Deposition) method, and a silicon nitride film 7 is deposited by the CVD method.
On silicon nitride film 7, a photoresist is applied, and the photoresist is formed to a desired pattern by photolithography. Using the resist pattern as a mask, silicon nitride film 7 is etched. Thereafter, the photoresist is removed, and as shown in FIG. 16, polycrystalline silicon film 6 is patterned using silicon nitride film 7 as a mask.
Thereafter, referring to FIG. 17, arsenic (As) is introduced obliquely to substrate 1, and thereafter annealing is performed in a nitrogen atmosphere. Thus, N+ diffusion layer 2 of a memory transistor is formed.
Thereafter, silicon nitride film 7 is removed by hot phosphoric acid, and the exposed portion of silicon oxide film 5 is etched by using an HF solution. At this time, silicon oxide film 5 immediately below polycrystalline silicon film 6 is left. Thereafter, as shown in FIG. 18, an interlayer insulating film 15 is deposited by the CVD method.
Thereafter, referring to FIG. 19, a phosphorus doped polycrystalline silicon film 18 is deposited by the CVD method. By etching back the phosphorus doped polycrystalline silicon film 18, polycrystalline silicon film 18 is left between polycrystalline silicon films 6, as shown in FIG. 20. The polycrystalline silicon film 18 serves as an access gate.
Thereafter, as shown in FIG. 21, the surface of the access gate is thermally oxidized, to form a silicon oxide film 19. Thereafter, a phosphorus doped polycrystalline silicon film is deposited by the CVD method, and thereafter a WSi film is deposited by the CVD method, to form conductive film 16 shown in FIG. 14. On conductive film 16, a silicon oxide film 17 is deposited by the CVD method.
By photolithography and etching, conductive film 16 and silicon oxide film 17 are patterned to form stripes. Thus, control gates are formed. Thereafter, using the patterned conductive film 16 and silicon oxide film 17, interlayer insulating film 15 is etched. Thereafter, using the patterned interlayer insulating film 15 as a mask, polycrystalline silicon film 6 is etched to form a floating gate. Thus, a non-volatile semiconductor memory device shown in FIG. 14 is obtained.
In the non-volatile semiconductor memory device having the above described structure, information is stored in the memory cell in accordance with whether the threshold voltage of the memory transistor is high with electrons introduced to the floating gate, or the threshold voltage of the memory transistor is low with the electrons discharged from the floating gate.
In the state where electrons are introduced to the floating gate, the threshold voltage of the memory transistor has a high value Vthp, which state is also referred to as a written state. The stored charges are retained semi-permanently as they are, and therefore, the stored information is also maintained semi-permanently.
In the state where the electrons are discharged from the floating gate, the threshold voltage of the memory transistor has a low value Vthe, which state is referred to as an erased state. By detecting these two states, the data stored in the memory cell can be read.
Now, the operation of writing data to mth memory transistor in a memory area will be described with reference to FIG. 22.
The mth memory transistor includes a control gate, a mth floating gate, a mth access gate, a mth N+ diffusion 2, a m+1th N+ diffusion layer 2 and substrate 1.
At the time of writing, referring to FIG. 22, a high voltage Vp (about 12V) is applied to the control gate, and substrate 1 is grounded. A voltage of 2V is applied to the mth access gate, while 0V is applied to the mxe2x88x921th and m+1th access gates. To mth N+ diffusion layer 2, 5V is applied, while 0V is applied to m+1th N+ diffusion layer 2.
Thus, hot electrons are generated in the channel of the mth memory transistor, and the electrons are introduced to the mth floating gate. As a result, the threshold voltage of the memory transistor increases.
At the time of erasure, a high voltage Ve (xe2x88x9220V) is applied to the control gate, and substrate 1, N+ diffusion layer 2 and the access gate are grounded. Thus, electrons are discharged by the tunneling phenomenon, from the floating gate to substrate 1. As a result, the threshold voltage of the memory transistor lowers.
At the time of reading of a selected mth memory transistor, 3.3V, for example, is applied to the control gate, and 3.3V is applied to the m+1th N+ diffusion layer 2, so that mth N+ diffusion layer and the substrate 1 are grounded. Here, when the values are set such that Vthp greater than 3.3V greater than Vthe, no current flows between the source and the drain of the memory transistor in the written state, while a current flows therebetween in the erased state.
The above described non-volatile semiconductor memory device, however, has the following problem. The problem will be described with reference to FIGS. 23A and 23B. In FIG. 23A, reference characters A, Axe2x80x2, B and C represent paths of arsenic ions.
As already described, when N+ diffusion layers 2 are formed, arsenic ions are introduced obliquely to substrate 1. Here, referring to FIG. 23A, in the paths A and Axe2x80x2, arsenic ions directly reach substrate 1, so that the concentration of the introduced arsenic at the surface of substrate 1 can be defined as Nxe2x80x2 sin xcex8 ((cmxe2x88x922).
When the introduction is along the path B, however, the arsenic ions are projected obliquely to polycrystalline silicon film 6. Here, arsenic ion must pass through the lower corner of polycrystalline silicon film 6 to reach substrate 1. Therefore, the amount of arsenic that reaches the substrate 1 is reduced as compared with the paths A and Axe2x80x2.
When the introduction is along the path C, arsenic ions introduced to substrate 1 are hindered by the silicon nitride film 7, and therefore the amount of arsenic reaching substrate 1 is reduced as compared with the paths A and Axe2x80x2, as in the case of the path B.
Therefore, as represented by xcex1 in FIG. 23A, for example, N+ diffusion layer 2 as the arsenic introduced region is formed with a concentration gradient. In FIG. 23B, the ordinate represents arsenic concentration at the surface of the substrate, while the abscissa represents position at the surface of the substrate.
When annealing is performed for 30 sec. in a nitrogen atmosphere at 850xc2x0 C. after the introduction of arsenic, the arsenic diffuses, of which distribution is as represented by xcex2 in FIG. 23B. Here, when the region having the arsenic concentration of at least 1xc3x971019 cmxe2x88x922 is defined as the N+ diffusion layer 2, then the width of the layer is X1.
As can be seen from FIG. 23B, the regions defined by xcex1 and xcex2 have almost trapezoidal shape, and the area of the regions become smaller than the area of a rectangular region. As the area of the regions represent the total amount of arsenic, that the area of the regions become smaller means that the total amount of arsenic introduced to N+ diffusion layer 2 is small. Therefore, the resistance value of N+ diffusion layer 2 becomes higher as compared with the size of N+ diffusion layer 2.
In order to increase the total amount of arsenic introduced to N+ diffusion layer 2 with the same amount of doping, it is necessary to attain such an arsenic distribution as represented by xcex3 in FIG. 23B, in which the width of the region having the arsenic concentration of at least 1xc3x971019 cmxe2x88x922 in N+ diffusion layer 2 must be increased to X2. Therefore, the size of N+ diffusion layer 2 must be enlarged.
When arsenic ions reach substrate 1 after passing through silicon oxide film 5 which will be the tunnel insulating film, silicon oxide film 5 is damaged. This results in degradation of rewriting characteristic or data retention of the non-volatile semiconductor memory device, decreasing reliability of the non-volatile semiconductor memory device.
Further, N+ diffusion layer 2 is formed below the access gate to a portion below the floating gate, as shown in FIG. 14. In order to form N+ diffusion layer 2 to extend up to the portion below the floating gate, it is necessary to set the arsenic ion implantation energy so that the arsenic ions can reach substrate 1 after passing through the lower corner of polycrystalline silicon film 6, or it is necessary to diffuse arsenic to the portion below the floating gate by thermal processing.
When the arsenic ions are caused to pass through the lower corner of polycrystalline silicon film 6, the problem of lower reliability of the non-volatile semiconductor memory device mentioned above results. When the arsenic is diffused to the portion below the floating gate by thermal processing, N+ diffusion layer 2 itself increases in size, making it difficult to miniaturize N+ diffusion layer 2.
The present invention was made to solve the above described problems. An object of the present invention is to improve performance of a memory transistor in a non-volatile semiconductor memory device.
Another object of the present invention is to improve reliability of a memory transistor in a non-volatile semiconductor memory device.
A still further object of the present invention is to improve performance of a memory transistor in a non-volatile semiconductor memory device, to improve reliability and to facilitate miniaturization.
According to an aspect, the present invention provides a non-volatile semiconductor memory device including: a semiconductor substrate of a first conductivity type having a main surface; first and second impurity diffusion layers of a second conductivity type of a first memory cell formed spaced from each other at the main surface of the semiconductor substrate; a floating gate of the first memory cell formed on a region between the first and second impurity diffusion layers with a first insulating film interposed; an access gate of the first memory cell formed adjacent to the floating gate on a region between the first and second impurity diffusion layers with a second insulating film interposed; a control gate of the first memory cell formed on the floating gate with a third insulating film interposed; and another access gate of a second memory cell provided at a position adjacent to the access gate of the first memory cell, with the second impurity diffusion layer positioned therebetween.
As a set of access gates are positioned adjacent with each other with the second impurity diffusion layer positioned therebetween, it becomes unnecessary to form the second impurity diffusion layer from below the access gate to a portion below the floating gate. Therefore, unlike the prior art example, it becomes unnecessary to introduce the impurity of the second conductivity type obliquely to the substrate. Thus, concentration gradient as observed in the prior art example in the second impurity diffusion layer can be suppressed. Further, the damage to the first insulating film can also be avoided. Further, it becomes unnecessary to diffuse the impurity of the second conductivity type from below the access gate to a portion below the floating gate.
According to another aspect, the present invention provides a non-volatile semiconductor memory device including: a semiconductor substrate of a first conductivity type having a main surface; first and second impurity diffusion layers of a second conductivity type of a first memory cell formed spaced from each other at the main surface of the semiconductor substrate; a floating gate of the first memory cell formed on a region between the first and second impurity diffusion layers with a first insulating film interposed; an access gate of the first memory cell formed adjacent to the floating gate on a region between the first and second impurity diffusion layers with a second insulating film interposed; a control gate of the first memory cell formed on the floating gate with a third insulating film interposed; another floating gate of a second memory cell provided at a position adjacent to the floating gate of the first memory cell with the first impurity diffusion layer positioned therebetween; and another control gate of the second memory cell formed on the aforementioned another floating gate, with a fourth insulating film interposed.
In this aspect, again, it becomes unnecessary to form the first impurity diffusion layer from below the floating gate to the portion below the access gate. Therefore, generation of the concentration gradient as observed in the prior art in the first impurity diffusion layer can be suppressed, and the damage to the first insulating film can also be avoided. Further, it becomes unnecessary to diffuse the impurity of the second conductivity type from below the floating gate to the portion below the access gate.
According to a still further aspect, the present invention provides a non-volatile semiconductor memory device including: a semiconductor substrate of a first conductivity type having a main surface; first and second impurity diffusion layers of a second conductivity type formed spaced from each other at the main surface of the semiconductor substrate; a floating gate formed on a region between the first and second impurity diffusion layers with a first insulating film interposed; an access gate having a sidewall shape formed adjacent to the floating gate on a region between the first and second impurity diffusion layers with a second insulating film interposed; and a control gate formed on the floating gate with a third insulating film interposed. Here, xe2x80x9csidewall shapexe2x80x9d refers to such a film shape that has a curved upper surface, such as the shape of the polycrystalline silicon film 9 shown in FIG. 1.
As the access gate is formed to have a sidewall shape, it becomes possible to form the access gate in a self-aligned manner with the floating gate. Thus, the memory size can be reduced.
Preferably, the non-volatile semiconductor memory device includes another floating gate provided at a position adjacent to the floating gate with a first impurity diffusion layer positioned therebetween, and another access gate having a sidewall shape provided at a position adjacent to the access gate with the second impurity diffusion layer positioned therebetween. Here, the first impurity diffusion layer is partially overlapped with the floating gate and the aforementioned another floating gate, while the second impurity diffusion layer is partially overlapped with the access gate and the aforementioned another access gate.
The method of manufacturing a non-volatile semiconductor memory device in accordance with the present invention includes the following steps. A non-volatile semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, first and second impurity diffusion layers of a second conductivity type formed spaced from each other at the main surface of the semiconductor substrate, a floating gate formed adjacent to the first impurity diffusion layer with a first insulating film on said main surface of said semiconductor substrate interposed, an access gate formed adjacent to the floating gate and the second impurity diffusion layer with a second insulating film on the main surface of said semiconductor substrate interposed, a control gate formed on the floating gate with a third insulating film interposed. The method includes the steps of forming a pattern of the floating gate including first conductive film on said main surface of a semiconductor substrate with the first insulating film interposed; forming a first impurity diffusion layer of a second conductivity type, using the pattern of the floating gate as a mask; forming the second insulating film and a pattern of the access gate including second conductive film; and forming a second impurity diffusion layer of a second conductivity type, using the pattern of the access gate as a mask.
As the first impurity diffusion layer of the second conductivity type is formed between the patterns of the floating gates using the patterns of the floating gates as a mask as described above, it becomes possible to form the first impurity diffusion layer in a self-aligned manner with the adjacent pattern of the floating gate, without the necessity of introducing the impurity obliquely as in the prior art example. Similarly, the second impurity diffusion layer can also be formed in a self-aligned manner with respect to the adjacent pattern of the access gate. Thus, the area occupied by the first and second impurity diffusion layers serving as the source or drain of the memory transistor can be reduced and the resistance can be reduced.
Preferably, the step of forming the first and second impurity diffusion layers includes the step of introducing the impurity of the second conductivity type to the main surface from a direction vertical to the main surface. Here, xe2x80x9cvertical directionxe2x80x9d includes a direction substantially vertical to the main surface. For example, an implantation angle inclined by 7xc2x0 from the vertical direction is considered substantially vertical.
As the impurity of the second conductivity type is introduced to the main surface from the direction vertical to the main surface, the concentration gradient of the first and second impurity diffusion layers can significantly be reduced as compared with the prior art. Further, the damage to the tunnel insulating film of the memory transistor caused by the impurity of the second conductivity type can be prevented.
Preferably, the step of forming the pattern of the access gate includes the step of forming a second insulating film to cover the pattern of the floating gate, forming a conductive film on the second insulating film, etching back the conductive film to leave the conductive film on sidewalls of the pattern of the floating gate, and removing the conductive film formed on one sidewall of the pattern of the floating gate.